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-- Company: 
-- Engineer: 
-- 
-- Create Date:	   18:33:41 04/07/2009 
-- Design Name: 
-- Module Name:	   MPC - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity MPC is
  port (CLK_IN	    : in  std_logic;
	 MBR_IN	    : in  std_logic_vector (7 downto 0);
	 Addr_IN    : in  std_logic_vector (8 downto 0);
	 JMPC_IN    : in  std_logic;
	 JAMZ_IN    : in  std_logic;
	 JAMN_IN    : in  std_logic;
	 N	    : in  std_logic;
	 Z	    : in  std_logic;
	 MIR_ADR_in : in  std_logic_vector(8 downto 0);
	 MPC_OUT    : out std_logic_vector(8 downto 0)
	 );
end MPC;

architecture Behavioral of MPC is
  signal N_Reg	 : std_logic;
  signal Z_Reg	 : std_logic;
  signal HighBit : std_logic;
  signal JAM_ADR : std_logic_vector(7 downto 0);
begin
  JAM_ADR <= MBR_IN(7 downto 0) or MIR_ADR_IN(7 downto 0);
  HighBit <= (JAMZ_IN and Z_Reg) or (JAMN_IN and N_Reg) or MIR_ADR_IN(8);
  with JMPC_IN select
    MPC_OUT <= HighBit & JAM_ADR     when '1',
    HighBit & MIR_ADR_IN(7 downto 0) when others;
  
  process(CLK_IN)
  begin
    if(CLK_IN = '1' and CLK_IN'event) then
      -- Latch Input
      N_REG <= N;
      Z_REG <= Z;
    end if;
  end process;
end Behavioral;

